The present invention relates to the field of digital integrated circuits and more particularly, to testing to verify the integrity of integrated circuit terminal pad input and output structures.
While an integrated circuit (IC) may have been thoroughly tested before being assembled onto a printed circuit board, a board level test is usually still needed to verify that the IC has not been damaged during assembly, for example, by electrostatic discharge, which may destroy the logic coupled to an input/output pad. It is also necessary to test at the board level to ensure that there are no shorts or open circuits on the I/O pads.
Known methods of testing for these failures generally involve providing a complex, time consuming, set of patterns to get the logic on the pads to desired states for testing purposes. For example, it is known to provide a serial scan path through an integrated circuit device for testing purposes. A carefully designed sequence of data is driven through the serial scan path to test logic functions. What is needed is a way to test receiver and driver logic on IC pads at the board level without requiring complex test patterns.
U.S. Pat. No. 4,896,296 discloses a programmable logic device which includes provision for a logic test mode of operation. During a logic test mode, data is serially loaded into a shift register latch ("SRL"). Under the control of a special test input signal, the data in the SRL is forced onto the sense amplifier inputs. This "apparent array pattern" is then sensed through the normal output logic and read out of a device output pin. Data can then be serially clocked out of the SRL and verified against the logical output that was received on the device output pins. This is an example of one way to test output logic circuitry in an integrated circuit. This technique, however, assumes that the serial data input and output pad structures function properly. The '296 patent does not disclose how to test input functionality of the device output pin. See FIGS. 1 and 5 and the text beginning at column 5, line 63, in the '296 patent.